/******************************************************************************
 ** File Name:      pinmap.h                                                  *
 ** Author:         Richard.Yang                                              *
 ** DATE:           03/08/2004                                                *
 ** Copyright:      2004 Spreatrum, Incoporated. All Rights Reserved.         *
 ** Description:    This file defines the structure of pin map.               *
 ******************************************************************************

 ******************************************************************************
 **                        Edit History                                       *
 ** ------------------------------------------------------------------------- *
 ** DATE           NAME             DESCRIPTION                               *
 ** 03/08/2004     Richard.Yang     Create.                                   *
 ******************************************************************************/

#ifndef _PINMAP_H_
#define _PINMAP_H_

#include <linux/types.h>
#include "sprd_reg.h"
#include "adi.h"

typedef struct {
	uint32_t reg;
	uint32_t val;
} pinmap_t;

int pin_init(void);

int pin_init_a0chip(void);

#if defined(CONFIG_SOC_IWHALE2)
#define CTL_PIN_BASE			(SPRD_PIN_BASE)

/* registers definitions for controller CTL_PIN */
#define REG_PIN_CTRL0                   ( 0x0000 )
#define REG_PIN_CTRL1                   ( 0x0004 )
#define REG_PIN_CTRL2                   ( 0x0008 )
#define REG_PIN_CTRL3                   ( 0x000c )
#define REG_PIN_CTRL4                   ( 0x0010 )
#define REG_PIN_CTRL5                   ( 0x0014 )
#define REG_PIN_CTRL6                   ( 0x0018 )
#define REG_PIN_CTRL7                   ( 0x001c )

/* registers definitions for controller CTL_PIN */
#define REG_PIN_RFCTL32            ( 0x0020 )
#define REG_PIN_RFCTL33            ( 0x0024 )
#define REG_PIN_RFCTL34            ( 0x0028 )
#define REG_PIN_RFCTL35            ( 0x002C )
#define REG_PIN_RFCTL36            ( 0x0030 )
#define REG_PIN_RFCTL37            ( 0x0034 )
#define REG_PIN_SPI0_CSN           ( 0x0038 )
#define REG_PIN_SPI0_DO            ( 0x003C )
#define REG_PIN_SPI0_DI            ( 0x0040 )
#define REG_PIN_SPI0_CLK           ( 0x0044 )
#define REG_PIN_USB30_CC_SWITCH    ( 0x0048 )
#define REG_PIN_U1TXD              ( 0x004C )
#define REG_PIN_U1RXD              ( 0x0050 )
#define REG_PIN_IIS1DI             ( 0x0054 )
#define REG_PIN_IIS1DO             ( 0x0058 )
#define REG_PIN_IIS1CLK            ( 0x005C )
#define REG_PIN_IIS1LRCK           ( 0x0060 )
#define REG_PIN_U2TXD              ( 0x0064 )
#define REG_PIN_U2RXD              ( 0x0068 )
#define REG_PIN_IIS3CLK            ( 0x006C )
#define REG_PIN_IIS3LRCK           ( 0x0070 )
#define REG_PIN_IIS3DI             ( 0x0074 )
#define REG_PIN_IIS3DO             ( 0x0078 )
#define REG_PIN_SD2_CMD            ( 0x007C )
#define REG_PIN_SD2_D0             ( 0x0080 )
#define REG_PIN_SD2_D1             ( 0x0084 )
#define REG_PIN_SD2_CLK            ( 0x0088 )
#define REG_PIN_SD2_D2             ( 0x008C )
#define REG_PIN_SD2_D3             ( 0x0090 )

#define REG_PIN_U4TXD              ( 0x0098 )
#define REG_PIN_U4RXD              ( 0x009C )
#define REG_PIN_DCDC_ARM_EN1       ( 0x00A0 )
#define REG_PIN_SENSOR_HUB_ACTION  ( 0x00A4 )
#define REG_PIN_PTEST              ( 0x00A8 )
#define REG_PIN_ANA_INT            ( 0x00AC )
#define REG_PIN_EXT_RST_B          ( 0x00B0 )
#define REG_PIN_AUD_SCLK           ( 0x00B4 )
#define REG_PIN_DCDC_ARM_EN0       ( 0x00B8 )
#define REG_PIN_CLK_32K            ( 0x00BC )
#define REG_PIN_CHIP_SLEEP         ( 0x00C0 )
#define REG_PIN_AUD_ADD0           ( 0x00C4 )
#define REG_PIN_AUD_DAD0           ( 0x00C8 )
#define REG_PIN_AUD_ADD1           ( 0x00CC )
#define REG_PIN_AUD_DAD1           ( 0x00D0 )
#define REG_PIN_AUD_SYNC           ( 0x00D4 )
#define REG_PIN_ADI_SCLK           ( 0x00D8 )
#define REG_PIN_ADI_D              ( 0x00DC )
#define REG_PIN_MTCK_ARM           ( 0x00E0 )
#define REG_PIN_MTMS_ARM           ( 0x00E4 )
#define REG_PIN_MTRST_N_ARM        ( 0x00E8 )
#define REG_PIN_MTDO_ARM           ( 0x00EC )
#define REG_PIN_MTDI_ARM           ( 0x00F0 )
#define REG_PIN_EXTINT16           ( 0x00F4 )
#define REG_PIN_KEYOUT0            ( 0x00F8 )
#define REG_PIN_KEYOUT1            ( 0x00FC )
#define REG_PIN_KEYOUT2            ( 0x0100 )
#define REG_PIN_KEYIN0             ( 0x0104 )
#define REG_PIN_KEYIN1             ( 0x0108 )
#define REG_PIN_KEYIN2             ( 0x010C )
#define REG_PIN_SD0_D0             ( 0x0110 )
#define REG_PIN_SD0_D1             ( 0x0114 )
#define REG_PIN_SD0_CLK0           ( 0x0118 )
#define REG_PIN_SD0_CMD            ( 0x011C )
#define REG_PIN_SD0_D2             ( 0x0120 )
#define REG_PIN_SD0_D3             ( 0x0124 )

#define REG_PIN_SIMCLK2            ( 0x012C )
#define REG_PIN_SIMDA2             ( 0x0130 )
#define REG_PIN_SIMRST2            ( 0x0134 )
#define REG_PIN_SIMCLK1            ( 0x0138 )
#define REG_PIN_SIMDA1             ( 0x013C )
#define REG_PIN_SIMRST1            ( 0x0140 )
#define REG_PIN_SIMCLK0            ( 0x0144 )
#define REG_PIN_SIMDA0             ( 0x0148 )
#define REG_PIN_SIMRST0            ( 0x014C )
#define REG_PIN_EMMC_CLK           ( 0x0150 )
#define REG_PIN_EMMC_RSTB          ( 0x0154 )
#define REG_PIN_EMMC_CMD           ( 0x0158 )
#define REG_PIN_EMMC_D0            ( 0x015C )
#define REG_PIN_EMMC_D1            ( 0x0160 )
#define REG_PIN_EMMC_D2            ( 0x0164 )
#define REG_PIN_EMMC_D3            ( 0x0168 )
#define REG_PIN_EMMC_D4            ( 0x016C )
#define REG_PIN_EMMC_D5            ( 0x0170 )
#define REG_PIN_EMMC_D6            ( 0x0174 )
#define REG_PIN_EMMC_D7            ( 0x0178 )
#define REG_PIN_EMMC_STROBE        ( 0x017C )

#define REG_PIN_SD1_CMD            ( 0x0184 )
#define REG_PIN_SD1_D0             ( 0x0188 )
#define REG_PIN_SD1_D1             ( 0x018C )
#define REG_PIN_SD1_CLK            ( 0x0190 )
#define REG_PIN_SD1_D2             ( 0x0194 )
#define REG_PIN_SD1_D3             ( 0x0198 )

#define REG_PIN_IIS0DI             ( 0x01A0 )
#define REG_PIN_IIS0DO             ( 0x01A4 )
#define REG_PIN_IIS0CLK            ( 0x01A8 )
#define REG_PIN_IIS0LRCK           ( 0x01AC )
#define REG_PIN_U3TXD              ( 0x01B0 )
#define REG_PIN_U3RXD              ( 0x01B4 )
#define REG_PIN_U3CTS              ( 0x01B8 )
#define REG_PIN_U3RTS              ( 0x01BC )
#define REG_PIN_U0TXD              ( 0x01C0 )
#define REG_PIN_U0RXD              ( 0x01C4 )
#define REG_PIN_U0CTS              ( 0x01C8 )
#define REG_PIN_U0RTS              ( 0x01CC )
#define REG_PIN_CLK_AUX0           ( 0x01D0 )
#define REG_PIN_RFCTL39            ( 0x01D4 )
#define REG_PIN_RFCTL38            ( 0x01D8 )
#define REG_PIN_WIFI_COEXIST       ( 0x01DC )
#define REG_PIN_BEIDOU_COEXIST     ( 0x01E0 )
#define REG_PIN_EXTINT12           ( 0x01E4 )
#define REG_PIN_EXTINT11           ( 0x01E8 )
#define REG_PIN_EXTINT10           ( 0x01EC )
#define REG_PIN_EXTINT9            ( 0x01F0 )
#define REG_PIN_EXTINT8            ( 0x01F4 )
#define REG_PIN_EXTINT7            ( 0x01F8 )
#define REG_PIN_EXTINT6            ( 0x01FC )
#define REG_PIN_SDA1               ( 0x0200 )
#define REG_PIN_SCL1               ( 0x0204 )
#define REG_PIN_EXTINT1            ( 0x0208 )
#define REG_PIN_EXTINT0            ( 0x020C )
#define REG_PIN_EXTINT5            ( 0x0210 )
#define REG_PIN_DSI_TE             ( 0x0214 )
#define REG_PIN_LCM_RSTN           ( 0x0218 )
#define REG_PIN_PWMA               ( 0x021C )
#define REG_PIN_SCL2               ( 0x0220 )
#define REG_PIN_SDA2               ( 0x0224 )
#define REG_PIN_CMPD1              ( 0x0228 )
#define REG_PIN_CMPD0              ( 0x022C )
#define REG_PIN_CMRST1             ( 0x0230 )
#define REG_PIN_CMRST0             ( 0x0234 )
#define REG_PIN_CMMCLK1            ( 0x0238 )
#define REG_PIN_CMMCLK             ( 0x023C )
#define REG_PIN_RFSEN0             ( 0x0240 )
#define REG_PIN_RFSCK0             ( 0x0244 )
#define REG_PIN_RFSDA0             ( 0x0248 )
#define REG_PIN_RFSEN1             ( 0x024C )
#define REG_PIN_RFSCK1             ( 0x0250 )
#define REG_PIN_RFSDA1             ( 0x0254 )
#define REG_PIN_RFCTL27            ( 0x0258 )
#define REG_PIN_RFCTL26            ( 0x025C )
#define REG_PIN_RFCTL31            ( 0x0260 )
#define REG_PIN_RFCTL30            ( 0x0264 )
#define REG_PIN_RF_LVDS0_ADC_ON    ( 0x0268 )
#define REG_PIN_RF_LVDS0_DAC_ON    ( 0x026C )
#define REG_PIN_RF_LVDS1_ADC_ON    ( 0x0270 )
#define REG_PIN_RF_LVDS1_DAC_ON    ( 0x0274 )
#define REG_PIN_SDA4               ( 0x0278 )
#define REG_PIN_SCL4               ( 0x027C )
#define REG_PIN_SDA0               ( 0x0280 )
#define REG_PIN_SCL0               ( 0x0284 )
#define REG_PIN_RFCTL29            ( 0x0288 )
#define REG_PIN_RFCTL28            ( 0x028C )
#define REG_PIN_RFFE0_SDA0         ( 0x0290 )
#define REG_PIN_RFFE0_SCK0         ( 0x0294 )
#define REG_PIN_RFFE1_SDA0         ( 0x0298 )
#define REG_PIN_RFFE1_SCK0         ( 0x029C )
#define REG_PIN_RFCTL0             ( 0x02A0 )
#define REG_PIN_RFCTL1             ( 0x02A4 )
#define REG_PIN_RFCTL2             ( 0x02A8 )
#define REG_PIN_RFCTL3             ( 0x02AC )
#define REG_PIN_RFCTL4             ( 0x02B0 )
#define REG_PIN_RFCTL5             ( 0x02B4 )
#define REG_PIN_RFCTL6             ( 0x02B8 )
#define REG_PIN_RFCTL7             ( 0x02BC )
#define REG_PIN_RFCTL8             ( 0x02C0 )
#define REG_PIN_RFCTL9             ( 0x02C4 )
#define REG_PIN_RFCTL10            ( 0x02C8 )
#define REG_PIN_RFCTL11            ( 0x02CC )
#define REG_PIN_RFCTL12            ( 0x02D0 )
#define REG_PIN_RFCTL13            ( 0x02D4 )
#define REG_PIN_RFCTL14            ( 0x02D8 )
#define REG_PIN_RFCTL15            ( 0x02DC )
#define REG_PIN_RFCTL16            ( 0x02E0 )
#define REG_PIN_RFCTL17            ( 0x02E4 )
#define REG_PIN_RFCTL18            ( 0x02E8 )
#define REG_PIN_RFCTL19            ( 0x02EC )
#define REG_PIN_RFCTL20            ( 0x02F0 )
#define REG_PIN_RFCTL21            ( 0x02F4 )
#define REG_PIN_RFCTL22            ( 0x02F8 )
#define REG_PIN_RFCTL23            ( 0x02FC )
#define REG_PIN_RFCTL24            ( 0x0300 )
#define REG_PIN_RFCTL25            ( 0x0304 )


/* registers definitions for controller CTL_PIN MISC_OFFSET */
#define REG_PIN_RFCTL32_MISC                ( 0x0420 )
#define REG_PIN_RFCTL33_MISC                ( 0x0424 )
#define REG_PIN_RFCTL34_MISC                ( 0x0428 )
#define REG_PIN_RFCTL35_MISC                ( 0x042C )
#define REG_PIN_RFCTL36_MISC                ( 0x0430 )
#define REG_PIN_RFCTL37_MISC                ( 0x0434 )
#define REG_PIN_SPI0_CSN_MISC               ( 0x0438 )
#define REG_PIN_SPI0_DO_MISC                ( 0x043C )
#define REG_PIN_SPI0_DI_MISC                ( 0x0440 )
#define REG_PIN_SPI0_CLK_MISC               ( 0x0444 )
#define REG_PIN_USB30_CC_SWITCH_MISC        ( 0x0448 )
#define REG_PIN_U1TXD_MISC                  ( 0x044C )
#define REG_PIN_U1RXD_MISC                  ( 0x0450 )
#define REG_PIN_IIS1DI_MISC                 ( 0x0454 )
#define REG_PIN_IIS1DO_MISC                 ( 0x0458 )
#define REG_PIN_IIS1CLK_MISC                ( 0x045C )
#define REG_PIN_IIS1LRCK_MISC               ( 0x0460 )
#define REG_PIN_U2TXD_MISC                  ( 0x0464 )
#define REG_PIN_U2RXD_MISC                  ( 0x0468 )
#define REG_PIN_IIS3CLK_MISC                ( 0x046C )
#define REG_PIN_IIS3LRCK_MISC               ( 0x0470 )
#define REG_PIN_IIS3DI_MISC                 ( 0x0474 )
#define REG_PIN_IIS3DO_MISC                 ( 0x0478 )
#define REG_PIN_SD2_CMD_MISC                ( 0x047C )
#define REG_PIN_SD2_D0_MISC                 ( 0x0480 )
#define REG_PIN_SD2_D1_MISC                 ( 0x0484 )
#define REG_PIN_SD2_CLK_MISC                ( 0x0488 )
#define REG_PIN_SD2_D2_MISC                 ( 0x048C )
#define REG_PIN_SD2_D3_MISC                 ( 0x0490 )
#define REG_PIN_SD2_DUMY_MISC               ( 0x0494 )
#define REG_PIN_U4TXD_MISC                  ( 0x0498 )
#define REG_PIN_U4RXD_MISC                  ( 0x049C )
#define REG_PIN_DCDC_ARM_EN1_MISC           ( 0x04A0 )
#define REG_PIN_SENSOR_HUB_ACTION_MISC      ( 0x04A4 )
#define REG_PIN_PTEST_MISC                  ( 0x04A8 )
#define REG_PIN_ANA_INT_MISC                ( 0x04AC )
#define REG_PIN_EXT_RST_B_MISC              ( 0x04B0 )
#define REG_PIN_AUD_SCLK_MISC               ( 0x04B4 )
#define REG_PIN_DCDC_ARM_EN0_MISC           ( 0x04B8 )
#define REG_PIN_CLK_32K_MISC                ( 0x04BC )
#define REG_PIN_CHIP_SLEEP_MISC             ( 0x04C0 )
#define REG_PIN_AUD_ADD0_MISC               ( 0x04C4 )
#define REG_PIN_AUD_DAD0_MISC               ( 0x04C8 )
#define REG_PIN_AUD_ADD1_MISC               ( 0x04CC )
#define REG_PIN_AUD_DAD1_MISC               ( 0x04D0 )
#define REG_PIN_AUD_SYNC_MISC               ( 0x04D4 )
#define REG_PIN_ADI_SCLK_MISC               ( 0x04D8 )
#define REG_PIN_ADI_D_MISC                  ( 0x04DC )
#define REG_PIN_MTCK_ARM_MISC               ( 0x04E0 )
#define REG_PIN_MTMS_ARM_MISC               ( 0x04E4 )
#define REG_PIN_MTRST_N_ARM_MISC            ( 0x04E8 )
#define REG_PIN_MTDO_ARM_MISC               ( 0x04EC )
#define REG_PIN_MTDI_ARM_MISC               ( 0x04F0 )
#define REG_PIN_EXTINT16_MISC               ( 0x04F4 )

#define REG_PIN_KEYOUT0_MISC                ( 0x04F8 ) 
#define REG_PIN_KEYOUT1_MISC                ( 0x04FC ) 
#define REG_PIN_KEYOUT2_MISC                ( 0x0500 ) 
#define REG_PIN_KEYIN0_MISC                 ( 0x0504 ) 
#define REG_PIN_KEYIN1_MISC                 ( 0x0508 ) 
#define REG_PIN_KEYIN2_MISC                 ( 0x050C ) 

#define REG_PIN_SD0_D0_MISC                 ( 0x0510 )
#define REG_PIN_SD0_D1_MISC                 ( 0x0514 )
#define REG_PIN_SD0_CLK0_MISC               ( 0x0518 )
#define REG_PIN_SD0_CMD_MISC                ( 0x051C )
#define REG_PIN_SD0_D2_MISC                 ( 0x0520 )
#define REG_PIN_SD0_D3_MISC                 ( 0x0524 )
#define REG_PIN_SD0_DUMY_MISC               ( 0x0528 )

#define REG_PIN_SIMCLK2_MISC                ( 0x052C )
#define REG_PIN_SIMDA2_MISC                 ( 0x0530 )
#define REG_PIN_SIMRST2_MISC                ( 0x0534 )
#define REG_PIN_SIMCLK1_MISC                ( 0x0538 )
#define REG_PIN_SIMDA1_MISC                 ( 0x053C )
#define REG_PIN_SIMRST1_MISC                ( 0x0540 )
#define REG_PIN_SIMCLK0_MISC                ( 0x0544 )
#define REG_PIN_SIMDA0_MISC                 ( 0x0548 )
#define REG_PIN_SIMRST0_MISC                ( 0x054C )

#define REG_PIN_EMMC_CLK_MISC               ( 0x0550 )
#define REG_PIN_EMMC_RSTB_MISC              ( 0x0554 )
#define REG_PIN_EMMC_CMD_MISC               ( 0x0558 )
#define REG_PIN_EMMC_D0_MISC                ( 0x055C )
#define REG_PIN_EMMC_D1_MISC                ( 0x0560 )
#define REG_PIN_EMMC_D2_MISC                ( 0x0564 )
#define REG_PIN_EMMC_D3_MISC                ( 0x0568 )
#define REG_PIN_EMMC_D4_MISC                ( 0x056C )
#define REG_PIN_EMMC_D5_MISC                ( 0x0570 )
#define REG_PIN_EMMC_D6_MISC                ( 0x0574 )
#define REG_PIN_EMMC_D7_MISC                ( 0x0578 )
#define REG_PIN_EMMC_STROBE_MISC            ( 0x057C )
#define REG_PIN_EMMC_DUMY_MISC              ( 0x0580 )
#define REG_PIN_SD1_CMD_MISC                ( 0x0584 )
#define REG_PIN_SD1_D0_MISC                 ( 0x0588 )
#define REG_PIN_SD1_D1_MISC                 ( 0x058C )
#define REG_PIN_SD1_CLK_MISC                ( 0x0590 )
#define REG_PIN_SD1_D2_MISC                 ( 0x0594 )
#define REG_PIN_SD1_D3_MISC                 ( 0x0598 )
#define REG_PIN_SD1_DUMY_MISC               ( 0x059C )
#define REG_PIN_IIS0DI_MISC                 ( 0x05A0 )
#define REG_PIN_IIS0DO_MISC                 ( 0x05A4 )
#define REG_PIN_IIS0CLK_MISC                ( 0x05A8 )
#define REG_PIN_IIS0LRCK_MISC               ( 0x05AC )
#define REG_PIN_U3TXD_MISC                  ( 0x05B0 )
#define REG_PIN_U3RXD_MISC                  ( 0x05B4 )

#define REG_PIN_U3CTS_MISC                  ( 0x05B8 )
#define REG_PIN_U3RTS_MISC                  ( 0x05BC )
#define REG_PIN_U0TXD_MISC                  ( 0x05C0 )
#define REG_PIN_U0RXD_MISC                  ( 0x05C4 )
#define REG_PIN_U0CTS_MISC                  ( 0x05C8 )
#define REG_PIN_U0RTS_MISC                  ( 0x05CC )
#define REG_PIN_CLK_AUX0_MISC               ( 0x05D0 )
#define REG_PIN_RFCTL39_MISC                ( 0x05D4 )
#define REG_PIN_RFCTL38_MISC                ( 0x05D8 )
#define REG_PIN_WIFI_COEXIST_MISC           ( 0x05DC )
#define REG_PIN_BEIDOU_COEXIST_MISC         ( 0x05E0 )
#define REG_PIN_EXTINT12_MISC               ( 0x05E4 )
#define REG_PIN_EXTINT11_MISC               ( 0x05E8 )
#define REG_PIN_EXTINT10_MISC               ( 0x05EC )
#define REG_PIN_EXTINT9_MISC                ( 0x05F0 )
#define REG_PIN_EXTINT8_MISC                ( 0x05F4 )
#define REG_PIN_EXTINT7_MISC                ( 0x05F8 )
#define REG_PIN_EXTINT6_MISC                ( 0x05FC )
#define REG_PIN_SDA1_MISC                   ( 0x0600 )
#define REG_PIN_SCL1_MISC                   ( 0x0604 )
#define REG_PIN_EXTINT1_MISC                ( 0x0608 )
#define REG_PIN_EXTINT0_MISC                ( 0x060C )
#define REG_PIN_EXTINT5_MISC                ( 0x0610 )
#define REG_PIN_DSI_TE_MISC                 ( 0x0614 )
#define REG_PIN_LCM_RSTN_MISC               ( 0x0618 )
#define REG_PIN_PWMA_MISC                   ( 0x061C )
#define REG_PIN_SCL2_MISC                   ( 0x0620 )
#define REG_PIN_SDA2_MISC                   ( 0x0624 )

#define REG_PIN_CMPD1_MISC                  ( 0x0628 )
#define REG_PIN_CMPD0_MISC                  ( 0x062C )
#define REG_PIN_CMRST1_MISC                 ( 0x0630 )
#define REG_PIN_CMRST0_MISC                 ( 0x0634 )
#define REG_PIN_CMMCLK1_MISC                ( 0x0638 )
#define REG_PIN_CMMCLK_MISC                 ( 0x063C )
#define REG_PIN_RFSEN0_MISC                 ( 0x0640 )
#define REG_PIN_RFSCK0_MISC                 ( 0x0644 )
#define REG_PIN_RFSDA0_MISC                 ( 0x0648 )
#define REG_PIN_RFSEN1_MISC                 ( 0x064C )
#define REG_PIN_RFSCK1_MISC                 ( 0x0650 )
#define REG_PIN_RFSDA1_MISC                 ( 0x0654 )
#define REG_PIN_RFCTL27_MISC                ( 0x0658 )
#define REG_PIN_RFCTL26_MISC                ( 0x065C )

#define REG_PIN_RFCTL31_MISC                ( 0x0660 )
#define REG_PIN_RFCTL30_MISC                ( 0x0664 )
#define REG_PIN_RF_LVDS0_ADC_ON_MISC        ( 0x0668 )
#define REG_PIN_RF_LVDS0_DAC_ON_MISC        ( 0x066C )
#define REG_PIN_RF_LVDS1_ADC_ON_MISC        ( 0x0670 )
#define REG_PIN_RF_LVDS1_DAC_ON_MISC        ( 0x0674 )
#define REG_PIN_SDA4_MISC                   ( 0x0678 )
#define REG_PIN_SCL4_MISC                   ( 0x067C )
#define REG_PIN_SDA0_MISC                   ( 0x0680 )
#define REG_PIN_SCL0_MISC                   ( 0x0684 )
#define REG_PIN_RFCTL29_MISC                ( 0x0688 )
#define REG_PIN_RFCTL28_MISC                ( 0x068C )
#define REG_PIN_RFFE0_SDA0_MISC             ( 0x0690 )
#define REG_PIN_RFFE0_SCK0_MISC             ( 0x0694 )
#define REG_PIN_RFFE1_SDA0_MISC             ( 0x0698 )
#define REG_PIN_RFFE1_SCK0_MISC             ( 0x069C )
#define REG_PIN_RFCTL0_MISC                 ( 0x06A0 )
#define REG_PIN_RFCTL1_MISC                 ( 0x06A4 )

#define REG_PIN_RFCTL2_MISC                 ( 0x06A8 )
#define REG_PIN_RFCTL3_MISC                 ( 0x06AC )
#define REG_PIN_RFCTL4_MISC                 ( 0x06B0 )
#define REG_PIN_RFCTL5_MISC                 ( 0x06B4 )
#define REG_PIN_RFCTL6_MISC                 ( 0x06B8 )
#define REG_PIN_RFCTL7_MISC                 ( 0x06BC )
#define REG_PIN_RFCTL8_MISC                 ( 0x06C0 )
#define REG_PIN_RFCTL9_MISC                 ( 0x06C4 )
#define REG_PIN_RFCTL10_MISC                ( 0x06C8 )
#define REG_PIN_RFCTL11_MISC                ( 0x06CC )
#define REG_PIN_RFCTL12_MISC                ( 0x06D0 )
#define REG_PIN_RFCTL13_MISC                ( 0x06D4 )
#define REG_PIN_RFCTL14_MISC                ( 0x06D8 )
#define REG_PIN_RFCTL15_MISC                ( 0x06DC )
#define REG_PIN_RFCTL16_MISC                ( 0x06E0 )
#define REG_PIN_RFCTL17_MISC                ( 0x06E4 )
#define REG_PIN_RFCTL18_MISC                ( 0x06E8 )
#define REG_PIN_RFCTL19_MISC                ( 0x06EC )
#define REG_PIN_RFCTL20_MISC                ( 0x06F0 )
#define REG_PIN_RFCTL21_MISC                ( 0x06F4 )
#define REG_PIN_RFCTL22_MISC                ( 0x06F8 )
#define REG_PIN_RFCTL23_MISC                ( 0x06FC )
#define REG_PIN_RFCTL24_MISC                ( 0x0700 )
#define REG_PIN_RFCTL25_MISC                ( 0x0704 )



/* bits definitions for register REG_PIN_XXX */
#define BITS_PIN_DS(_x_)                ( ((_x_) << 19) & (BIT_19|BIT_20|BIT_21) )
#define BIT_PIN_SLP_AGCP                ( BIT_16 )
#define BIT_PIN_SLP_WTLCP               ( BIT_15 )
#define BIT_PIN_SLP_PUBCP               ( BIT_14 )
#define BIT_PIN_SLP_AP                  ( BIT_13 )
#define BIT_PIN_SLP_NONE		( (~(0xf << 13)) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_ISO_VALUE		( BIT_8 )
#define BIT_PIN_WPU                     ( BIT_7 )
#define BIT_PIN_WPD                     ( BIT_6 )
#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_PIN_SLP_WPU                 ( BIT_3 )
#define BIT_PIN_SLP_WPD                 ( BIT_2 )
#define BIT_PIN_SLP_IE                  ( BIT_1 )
#define BIT_PIN_SLP_OE                  ( BIT_0 )

/* vars definitions for controller CTL_PIN */
#define BIT_PIN_NUL                     ( 0 )
#define BIT_PIN_SLP_NUL                 ( 0 )
#define BIT_PIN_SLP_Z                   ( 0 )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPUS                    ( BIT_12 )
#define BIT_PIN_NULL                    ( 0 )


// CFIO --------
#define BITS_DEF(_x_)		    ( ((_x_) << 22) & (BIT_22|BIT_23|BIT_24|BIT_25|BIT_26|BIT_27|BIT_28|BIT_29) )//BIT22~BIT29 keep default value
//#define BITS_HYSCTL(_x_)		( ((_x_) << 28) & (BIT_28|BIT_29) )//CFIO
//#define BIT_NSTATICEN		    ( BIT_27 )//CFIO
//#define BIT_PSTATICEN		    ( BIT_26 )//CFIO
//#define BITS_NSLEW(_x_)		    ( ((_x_) << 24) & (BIT_24|BIT_25) )//CFIO
//#define BITS_PSLEW(_x_)		    ( ((_x_) << 22) & (BIT_22|BIT_23) )//CFIO
//#define BITS_NSTR(_x_)		( ((_x_) << 20) & (BIT_20|BIT_21) )
//#define BITS_PSTR(_x_)		( ((_x_) << 18) & (BIT_18|BIT_19) )
#define BITS_STR(_x_)				((((_x_) << 18) & (BIT_18|BIT_19))|(((_x_) << 20) & (BIT_20|BIT_21)))//CFIO
#define BIT_SLP_AGCP                ( BIT_16 )
#define BIT_SLP_WTLCP               ( BIT_15 )
#define BIT_SLP_PUBCP               ( BIT_14 )
#define BIT_SLP_AP                  ( BIT_13 )
#define BIT_SLP_NONE		( (~(0xf << 13)) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BIT_WPUS		        ( BIT_12 )
#define BIT_WPD2                ( BIT_11 )
#define BIT_WPUS2               ( BIT_10 )
#define BIT_POC				    ( BIT_9 )
#define BIT_ISO_VALUE		    ( BIT_8 )
#define BIT_WPU			( BIT_7 )
#define BIT_WPD 		( BIT_6 )
#define BITS_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_SLP_WPU                 ( BIT_3 )
#define BIT_SLP_WPD                 ( BIT_2 )
#define BIT_SLP_IE                  ( BIT_1 )
#define BIT_SLP_OE                  ( BIT_0 )
#define BIT_SLP_NUL                   ( 0 )
#define BIT_NUL                     ( 0 )
#define BIT_SLP_Z                   ( 0 )

#elif defined(CONFIG_SPRD_SOC_SP9853I)

#define CENTRAL_PIN_REG_BASE			(SPRD_PIN_BASE)

#define G1_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x1000 )
#define G2_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x2000 )
#define G3_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x3000 )
#define G4_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x4000 )
#define G5_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x5000 )
#define G6_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x6000 )
#define G7_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x7000 )
#define G8_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x8000 )
#define G9_PIN_REG_BASE				( CENTRAL_PIN_REG_BASE + 0x9000 )
#define G10_PIN_REG_BASE			( CENTRAL_PIN_REG_BASE + 0xA000 )
#define G11_PIN_REG_BASE			( CENTRAL_PIN_REG_BASE + 0xB000 )
#define G12_PIN_REG_BASE			( CENTRAL_PIN_REG_BASE + 0xC000 )
#define G13_PIN_REG_BASE			( CENTRAL_PIN_REG_BASE + 0xD000 )

/* registers definitions for controller CTL_PIN */
#define REG_PIN_CTRL_REG0				( CENTRAL_PIN_REG_BASE + 0x0000 )
#define REG_PIN_CTRL_REG1				( CENTRAL_PIN_REG_BASE + 0x0004 )
#define REG_PIN_CTRL_REG2				( CENTRAL_PIN_REG_BASE + 0x0008 )
#define REG_PIN_CTRL_REG3				( CENTRAL_PIN_REG_BASE + 0x000C )
#define REG_PIN_CTRL_REG4				( CENTRAL_PIN_REG_BASE + 0x0010 )
#define REG_PIN_CTRL_REG5				( CENTRAL_PIN_REG_BASE + 0x0014 )
#define REG_PIN_CTRL_REG6				( CENTRAL_PIN_REG_BASE + 0x0018 )
#define REG_PIN_CTRL_REG7				( CENTRAL_PIN_REG_BASE + 0x001C )

/* registers definitions for controller CENTRAL PIN */
#define REG_PIN_SD0_D0				( CENTRAL_PIN_REG_BASE + 0x0020 )
#define REG_PIN_SD0_D1				( CENTRAL_PIN_REG_BASE + 0x0024 )
#define REG_PIN_SD0_CLK0          		( CENTRAL_PIN_REG_BASE + 0x0028 )
#define REG_PIN_SD0_CMD           		( CENTRAL_PIN_REG_BASE + 0x002C )
#define REG_PIN_SD0_D2            		( CENTRAL_PIN_REG_BASE + 0x0030 )
#define REG_PIN_SD0_D3            		( CENTRAL_PIN_REG_BASE + 0x0034 )
#define REG_PIN_EXTINT5           		( CENTRAL_PIN_REG_BASE + 0x003C )
#define REG_PIN_EXTINT6           		( CENTRAL_PIN_REG_BASE + 0x0040 )
#define REG_PIN_EXT_RST_B         		( CENTRAL_PIN_REG_BASE + 0x0044 )
#define REG_PIN_AUD_SCLK          		( CENTRAL_PIN_REG_BASE + 0x0048 )
#define REG_PIN_DCDC_ARM_EN0      		( CENTRAL_PIN_REG_BASE + 0x004C )
#define REG_PIN_CLK_32K           		( CENTRAL_PIN_REG_BASE + 0x0050 )
#define REG_PIN_CHIP_SLEEP        		( CENTRAL_PIN_REG_BASE + 0x0054 )
#define REG_PIN_AUD_ADD0          		( CENTRAL_PIN_REG_BASE + 0x0058 )
#define REG_PIN_AUD_DAD0          		( CENTRAL_PIN_REG_BASE + 0x005C )
#define REG_PIN_AUD_ADSYNC        		( CENTRAL_PIN_REG_BASE + 0x0060 )
#define REG_PIN_AUD_DAD1          		( CENTRAL_PIN_REG_BASE + 0x0064 )
#define REG_PIN_AUD_DASYNC        		( CENTRAL_PIN_REG_BASE + 0x0068 )
#define REG_PIN_ADI_SCLK          		( CENTRAL_PIN_REG_BASE + 0x006C )
#define REG_PIN_ADI_D             		( CENTRAL_PIN_REG_BASE + 0x0070 )
#define REG_PIN_DCDC_ARM_EN1      		( CENTRAL_PIN_REG_BASE + 0x0074 )
#define REG_PIN_SENSOR_HUB_ACTION 		( CENTRAL_PIN_REG_BASE + 0x0078 )
#define REG_PIN_PTEST             		( CENTRAL_PIN_REG_BASE + 0x007C )
#define REG_PIN_ANA_INT           		( CENTRAL_PIN_REG_BASE + 0x0080 )
#define REG_PIN_DSI_TE            		( CENTRAL_PIN_REG_BASE + 0x0084 )
#define REG_PIN_LCM_RSTN          		( CENTRAL_PIN_REG_BASE + 0x0088 )
#define REG_PIN_PWMA              		( CENTRAL_PIN_REG_BASE + 0x008C )
#define REG_PIN_EXTINT10          		( CENTRAL_PIN_REG_BASE + 0x0090 )
#define REG_PIN_EXTINT9           		( CENTRAL_PIN_REG_BASE + 0x0094 )
#define REG_PIN_EMMC_CLK          		( CENTRAL_PIN_REG_BASE + 0x0098 )
#define REG_PIN_EMMC_RSTB         		( CENTRAL_PIN_REG_BASE + 0x009C )
#define REG_PIN_EMMC_CMD          		( CENTRAL_PIN_REG_BASE + 0x00A0 )
#define REG_PIN_EMMC_D0           		( CENTRAL_PIN_REG_BASE + 0x00A4 )
#define REG_PIN_EMMC_D1           		( CENTRAL_PIN_REG_BASE + 0x00A8 )
#define REG_PIN_EMMC_D2           		( CENTRAL_PIN_REG_BASE + 0x00AC )
#define REG_PIN_EMMC_D3           		( CENTRAL_PIN_REG_BASE + 0x00B0 )
#define REG_PIN_EMMC_D4           		( CENTRAL_PIN_REG_BASE + 0x00B4 )
#define REG_PIN_EMMC_D5           		( CENTRAL_PIN_REG_BASE + 0x00B8 )
#define REG_PIN_EMMC_D6           		( CENTRAL_PIN_REG_BASE + 0x00BC )
#define REG_PIN_EMMC_D7           		( CENTRAL_PIN_REG_BASE + 0x00C0 )
#define REG_PIN_EMMC_STROBE       		( CENTRAL_PIN_REG_BASE + 0x00C4 )
#define REG_PIN_EXTINT11          		( CENTRAL_PIN_REG_BASE + 0x00CC )
#define REG_PIN_EXTINT7           		( CENTRAL_PIN_REG_BASE + 0x00D0 )
#define REG_PIN_EXTINT8           		( CENTRAL_PIN_REG_BASE + 0x00D4 )
#define REG_PIN_SD1_CMD           		( CENTRAL_PIN_REG_BASE + 0x00D8 )
#define REG_PIN_SD1_D0            		( CENTRAL_PIN_REG_BASE + 0x00DC )
#define REG_PIN_SD1_D1            		( CENTRAL_PIN_REG_BASE + 0x00E0 )
#define REG_PIN_SD1_CLK           		( CENTRAL_PIN_REG_BASE + 0x00E4 )
#define REG_PIN_SD1_D2            		( CENTRAL_PIN_REG_BASE + 0x00E8 )
#define REG_PIN_SD1_D3            		( CENTRAL_PIN_REG_BASE + 0x00EC )
#define REG_PIN_U0TXD             		( CENTRAL_PIN_REG_BASE + 0x00F4 )
#define REG_PIN_U0RXD             		( CENTRAL_PIN_REG_BASE + 0x00F8 )
#define REG_PIN_U0CTS             		( CENTRAL_PIN_REG_BASE + 0x00FC )
#define REG_PIN_U0RTS             		( CENTRAL_PIN_REG_BASE + 0x0100 )
#define REG_PIN_IIS0DI            		( CENTRAL_PIN_REG_BASE + 0x0104 )
#define REG_PIN_IIS0DO            		( CENTRAL_PIN_REG_BASE + 0x0108 )
#define REG_PIN_IIS0CLK           		( CENTRAL_PIN_REG_BASE + 0x010C )
#define REG_PIN_IIS0LRCK          		( CENTRAL_PIN_REG_BASE + 0x0110 )
#define REG_PIN_CLK_AUX0          		( CENTRAL_PIN_REG_BASE + 0x0114 )
#define REG_PIN_RFCTL19           		( CENTRAL_PIN_REG_BASE + 0x0118 )
#define REG_PIN_RFCTL18           		( CENTRAL_PIN_REG_BASE + 0x011C )
#define REG_PIN_WIFI_COEXIST      		( CENTRAL_PIN_REG_BASE + 0x0120 )
#define REG_PIN_BEIDOU_COEXIST    		( CENTRAL_PIN_REG_BASE + 0x0124 )
#define REG_PIN_MTCK_ARM          		( CENTRAL_PIN_REG_BASE + 0x0128 )
#define REG_PIN_MTMS_ARM          		( CENTRAL_PIN_REG_BASE + 0x012C )
#define REG_PIN_MTRST_N_ARM       		( CENTRAL_PIN_REG_BASE + 0x0130 )
#define REG_PIN_MTDO_ARM          		( CENTRAL_PIN_REG_BASE + 0x0134 )
#define REG_PIN_MTDI_ARM          		( CENTRAL_PIN_REG_BASE + 0x0138 )
#define REG_PIN_U3TXD             		( CENTRAL_PIN_REG_BASE + 0x013C )
#define REG_PIN_U3RXD             		( CENTRAL_PIN_REG_BASE + 0x0140 )
#define REG_PIN_U3CTS             		( CENTRAL_PIN_REG_BASE + 0x0144 )
#define REG_PIN_U3RTS             		( CENTRAL_PIN_REG_BASE + 0x0148 )
#define REG_PIN_KEYOUT0           		( CENTRAL_PIN_REG_BASE + 0x014C )
#define REG_PIN_KEYOUT1           		( CENTRAL_PIN_REG_BASE + 0x0150 )
#define REG_PIN_KEYOUT2           		( CENTRAL_PIN_REG_BASE + 0x0154 )
#define REG_PIN_KEYIN0            		( CENTRAL_PIN_REG_BASE + 0x0158 )
#define REG_PIN_KEYIN1            		( CENTRAL_PIN_REG_BASE + 0x015C )
#define REG_PIN_KEYIN2            		( CENTRAL_PIN_REG_BASE + 0x0160 )
#define REG_PIN_SDA1              		( CENTRAL_PIN_REG_BASE + 0x0164 )
#define REG_PIN_SCL1              		( CENTRAL_PIN_REG_BASE + 0x0168 )
#define REG_PIN_EXTINT1           		( CENTRAL_PIN_REG_BASE + 0x016C )
#define REG_PIN_EXTINT0           		( CENTRAL_PIN_REG_BASE + 0x0170 )
#define REG_PIN_EXTINT12          		( CENTRAL_PIN_REG_BASE + 0x0174 )
#define REG_PIN_EXTINT15          		( CENTRAL_PIN_REG_BASE + 0x0178 )
#define REG_PIN_CMPD1             		( CENTRAL_PIN_REG_BASE + 0x017C )
#define REG_PIN_CMPD0             		( CENTRAL_PIN_REG_BASE + 0x0180 )
#define REG_PIN_CMRST1            		( CENTRAL_PIN_REG_BASE + 0x0184 )
#define REG_PIN_CMRST0            		( CENTRAL_PIN_REG_BASE + 0x0188 )
#define REG_PIN_CMMCLK1           		( CENTRAL_PIN_REG_BASE + 0x018C )
#define REG_PIN_CMMCLK            		( CENTRAL_PIN_REG_BASE + 0x0190 )
#define REG_PIN_SDA0              		( CENTRAL_PIN_REG_BASE + 0x0194 )
#define REG_PIN_SCL0              		( CENTRAL_PIN_REG_BASE + 0x0198 )
#define REG_PIN_RFSEN0            		( CENTRAL_PIN_REG_BASE + 0x019C )
#define REG_PIN_RFSCK0            		( CENTRAL_PIN_REG_BASE + 0x01A0 )
#define REG_PIN_RFSDA0            		( CENTRAL_PIN_REG_BASE + 0x01A4 )
#define REG_PIN_RFSEN1            		( CENTRAL_PIN_REG_BASE + 0x01A8 )
#define REG_PIN_RFSCK1            		( CENTRAL_PIN_REG_BASE + 0x01AC )
#define REG_PIN_RFSDA1            		( CENTRAL_PIN_REG_BASE + 0x01B0 )
#define REG_PIN_RFFE0_SDA         		( CENTRAL_PIN_REG_BASE + 0x01B4 )
#define REG_PIN_RFFE0_SCK         		( CENTRAL_PIN_REG_BASE + 0x01B8 )
#define REG_PIN_RFFE1_SDA         		( CENTRAL_PIN_REG_BASE + 0x01BC )
#define REG_PIN_RFFE1_SCK         		( CENTRAL_PIN_REG_BASE + 0x01C0 )
#define REG_PIN_RF_LVDS0_DAC_ON   		( CENTRAL_PIN_REG_BASE + 0x01C4 )
#define REG_PIN_RF_LVDS0_ADC_ON   		( CENTRAL_PIN_REG_BASE + 0x01C8 )
#define REG_PIN_RFCTL0            		( CENTRAL_PIN_REG_BASE + 0x01CC )
#define REG_PIN_RFCTL1            		( CENTRAL_PIN_REG_BASE + 0x01D0 )
#define REG_PIN_RFCTL2            		( CENTRAL_PIN_REG_BASE + 0x01D4 )
#define REG_PIN_RFCTL3            		( CENTRAL_PIN_REG_BASE + 0x01D8 )
#define REG_PIN_RFCTL4            		( CENTRAL_PIN_REG_BASE + 0x01DC )
#define REG_PIN_RFCTL5            		( CENTRAL_PIN_REG_BASE + 0x01E0 )
#define REG_PIN_RFCTL6            		( CENTRAL_PIN_REG_BASE + 0x01E4 )
#define REG_PIN_RFCTL7            		( CENTRAL_PIN_REG_BASE + 0x01E8 )
#define REG_PIN_RFCTL8            		( CENTRAL_PIN_REG_BASE + 0x01EC )
#define REG_PIN_RFCTL9            		( CENTRAL_PIN_REG_BASE + 0x01F0 )
#define REG_PIN_RFCTL10           		( CENTRAL_PIN_REG_BASE + 0x01F4 )
#define REG_PIN_RFCTL11           		( CENTRAL_PIN_REG_BASE + 0x01F8 )
#define REG_PIN_RFCTL12           		( CENTRAL_PIN_REG_BASE + 0x01FC )
#define REG_PIN_RFCTL13           		( CENTRAL_PIN_REG_BASE + 0x0200 )
#define REG_PIN_RFCTL14           		( CENTRAL_PIN_REG_BASE + 0x0204 )
#define REG_PIN_RFCTL15           		( CENTRAL_PIN_REG_BASE + 0x0208 )
#define REG_PIN_RFCTL16           		( CENTRAL_PIN_REG_BASE + 0x020C )
#define REG_PIN_RFCTL17           		( CENTRAL_PIN_REG_BASE + 0x0210 )
#define REG_PIN_SD2_CMD           		( CENTRAL_PIN_REG_BASE + 0x0214 )
#define REG_PIN_SD2_D0            		( CENTRAL_PIN_REG_BASE + 0x0218 )
#define REG_PIN_SD2_D1            		( CENTRAL_PIN_REG_BASE + 0x021C )
#define REG_PIN_SD2_CLK           		( CENTRAL_PIN_REG_BASE + 0x0220 )
#define REG_PIN_SD2_D2            		( CENTRAL_PIN_REG_BASE + 0x0224 )
#define REG_PIN_SD2_D3            		( CENTRAL_PIN_REG_BASE + 0x0228 )
#define REG_PIN_U4TXD             		( CENTRAL_PIN_REG_BASE + 0x0230 )
#define REG_PIN_U4RXD             		( CENTRAL_PIN_REG_BASE + 0x0234 )
#define REG_PIN_U2TXD             		( CENTRAL_PIN_REG_BASE + 0x0238 )
#define REG_PIN_U2RXD             		( CENTRAL_PIN_REG_BASE + 0x023C )
#define REG_PIN_U1TXD             		( CENTRAL_PIN_REG_BASE + 0x0240 )
#define REG_PIN_U1RXD             		( CENTRAL_PIN_REG_BASE + 0x0244 )
#define REG_PIN_SDA4              		( CENTRAL_PIN_REG_BASE + 0x0248 )
#define REG_PIN_SCL4              		( CENTRAL_PIN_REG_BASE + 0x024C )
#define REG_PIN_SCL2              		( CENTRAL_PIN_REG_BASE + 0x0250 )
#define REG_PIN_SDA2              		( CENTRAL_PIN_REG_BASE + 0x0254 )
#define REG_PIN_IIS3DI            		( CENTRAL_PIN_REG_BASE + 0x0258 )
#define REG_PIN_IIS3DO            		( CENTRAL_PIN_REG_BASE + 0x025C )
#define REG_PIN_IIS3CLK           		( CENTRAL_PIN_REG_BASE + 0x0260 )
#define REG_PIN_IIS3LRCK          		( CENTRAL_PIN_REG_BASE + 0x0264 )
#define REG_PIN_IIS1DI            		( CENTRAL_PIN_REG_BASE + 0x0268 )
#define REG_PIN_IIS1DO            		( CENTRAL_PIN_REG_BASE + 0x026C )
#define REG_PIN_IIS1CLK           		( CENTRAL_PIN_REG_BASE + 0x0270 )
#define REG_PIN_IIS1LRCK          		( CENTRAL_PIN_REG_BASE + 0x0274 )
#define REG_PIN_SPI0_CSN          		( CENTRAL_PIN_REG_BASE + 0x0278 )
#define REG_PIN_SPI0_DO           		( CENTRAL_PIN_REG_BASE + 0x027C )
#define REG_PIN_SPI0_DI           		( CENTRAL_PIN_REG_BASE + 0x0280 )
#define REG_PIN_SPI0_CLK          		( CENTRAL_PIN_REG_BASE + 0x0284 )
#define REG_PIN_SIMCLK2           		( CENTRAL_PIN_REG_BASE + 0x0288 )
#define REG_PIN_SIMDA2            		( CENTRAL_PIN_REG_BASE + 0x028C )
#define REG_PIN_SIMRST2           		( CENTRAL_PIN_REG_BASE + 0x0290 )
#define REG_PIN_SIMCLK1           		( CENTRAL_PIN_REG_BASE + 0x0294 )
#define REG_PIN_SIMDA1            		( CENTRAL_PIN_REG_BASE + 0x0298 )
#define REG_PIN_SIMRST1           		( CENTRAL_PIN_REG_BASE + 0x029C )
#define REG_PIN_SIMCLK0           		( CENTRAL_PIN_REG_BASE + 0x02A0 )
#define REG_PIN_SIMDA0            		( CENTRAL_PIN_REG_BASE + 0x02A4 )
#define REG_PIN_SIMRST0           		( CENTRAL_PIN_REG_BASE + 0x02A8 )

/* registers definitions for controller GROUP PIN */
#define REG_GROUP_PIN_SD0_D0                    ( G1_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_SD0_D1                    ( G1_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_SD0_CLK0                  ( G1_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_SD0_CMD                   ( G1_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_SD0_D2                    ( G1_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_SD0_D3                    ( G1_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SD_MS                     ( G1_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_SD0_D0_SET                ( G1_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_SD0_D1_SET                ( G1_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_SD0_CLK0_SET              ( G1_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_SD0_CMD_SET               ( G1_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_SD0_D2_SET                ( G1_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_SD0_D3_SET                ( G1_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SD_MS_SET                 ( G1_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_SD0_D0_CLR                ( G1_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_SD0_D1_CLR                ( G1_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_SD0_CLK0_CLR              ( G1_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_SD0_CMD_CLR               ( G1_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_SD0_D2_CLR                ( G1_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_SD0_D3_CLR                ( G1_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_SD_MS_CLR                 ( G1_PIN_REG_BASE + 0x081C )

#define REG_GROUP_PIN_EXTINT5                   ( G2_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_EXTINT6                   ( G2_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_EXT_RST_B                 ( G2_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_AUD_SCLK                  ( G2_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_DCDC_ARM_EN0              ( G2_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_CLK_32K                   ( G2_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_CHIP_SLEEP                ( G2_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_AUD_ADD0                  ( G2_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_AUD_DAD0                  ( G2_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_AUD_ADSYNC                ( G2_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_AUD_DAD1                  ( G2_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_AUD_DASYNC                ( G2_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_ADI_SCLK                  ( G2_PIN_REG_BASE + 0x0030 )
#define REG_GROUP_PIN_ADI_D                     ( G2_PIN_REG_BASE + 0x0034 )
#define REG_GROUP_PIN_DCDC_ARM_EN1              ( G2_PIN_REG_BASE + 0x0038 )
#define REG_GROUP_PIN_SENSOR_HUB_ACTION         ( G2_PIN_REG_BASE + 0x003C )
#define REG_GROUP_PIN_PTEST                     ( G2_PIN_REG_BASE + 0x0040 )
#define REG_GROUP_PIN_ANA_INT                   ( G2_PIN_REG_BASE + 0x0044 )
#define REG_GROUP_PIN_EXTINT5_SET               ( G2_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_EXTINT6_SET               ( G2_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_EXT_RST_B_SET             ( G2_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_AUD_SCLK_SET              ( G2_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_DCDC_ARM_EN0_SET          ( G2_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_CLK_32K_SET               ( G2_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_CHIP_SLEEP_SET            ( G2_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_AUD_ADD0_SET              ( G2_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_AUD_DAD0_SET              ( G2_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_AUD_ADSYNC_SET            ( G2_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_AUD_DAD1_SET              ( G2_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_AUD_DASYNC_SET            ( G2_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_ADI_SCLK_SET              ( G2_PIN_REG_BASE + 0x0430 )
#define REG_GROUP_PIN_ADI_D_SET                 ( G2_PIN_REG_BASE + 0x0434 )
#define REG_GROUP_PIN_DCDC_ARM_EN1_SET          ( G2_PIN_REG_BASE + 0x0438 )
#define REG_GROUP_PIN_SENSOR_HUB_ACTION_SET     ( G2_PIN_REG_BASE + 0x043C )
#define REG_GROUP_PIN_PTEST_SET                 ( G2_PIN_REG_BASE + 0x0440 )
#define REG_GROUP_PIN_ANA_INT_SET               ( G2_PIN_REG_BASE + 0x0444 )
#define REG_GROUP_PIN_EXTINT5_CLR               ( G2_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_EXTINT6_CLR               ( G2_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_EXT_RST_B_CLR             ( G2_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_AUD_SCLK_CLR              ( G2_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_DCDC_ARM_EN0_CLR          ( G2_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_CLK_32K_CLR               ( G2_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_CHIP_SLEEP_CLR            ( G2_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_AUD_ADD0_CLR              ( G2_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_AUD_DAD0_CLR              ( G2_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_AUD_ADSYNC_CLR            ( G2_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_AUD_DAD1_CLR              ( G2_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_AUD_DASYNC_CLR            ( G2_PIN_REG_BASE + 0x082C )
#define REG_GROUP_PIN_ADI_SCLK_CLR              ( G2_PIN_REG_BASE + 0x0830 )
#define REG_GROUP_PIN_ADI_D_CLR                 ( G2_PIN_REG_BASE + 0x0834 )
#define REG_GROUP_PIN_DCDC_ARM_EN1_CLR          ( G2_PIN_REG_BASE + 0x0838 )
#define REG_GROUP_PIN_SENSOR_HUB_ACTION_CLR     ( G2_PIN_REG_BASE + 0x083C )
#define REG_GROUP_PIN_PTEST_CLR                 ( G2_PIN_REG_BASE + 0x0840 )
#define REG_GROUP_PIN_ANA_INT_CLR               ( G2_PIN_REG_BASE + 0x0844 )

#define REG_GROUP_PIN_DSI_TE                    ( G3_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_LCM_RSTN                  ( G3_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_PWMA                      ( G3_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_EXTINT10                  ( G3_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_EXTINT9                   ( G3_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_DSI_TE_SET                ( G3_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_LCM_RSTN_SET              ( G3_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_PWMA_SET                  ( G3_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_EXTINT10_SET              ( G3_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_EXTINT9_SET               ( G3_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_DSI_TE_CLR                ( G3_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_LCM_RSTN_CLR              ( G3_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_PWMA_CLR                  ( G3_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_EXTINT10_CLR              ( G3_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_EXTINT9_CLR               ( G3_PIN_REG_BASE + 0x0810 )

#define REG_GROUP_PIN_EMMC_CLK                  ( G4_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_EMMC_RSTB                 ( G4_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_EMMC_CMD                  ( G4_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_EMMC_D0                   ( G4_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_EMMC_D1                   ( G4_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_EMMC_D2                   ( G4_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_EMMC_D3                   ( G4_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_EMMC_D4                   ( G4_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_EMMC_D5                   ( G4_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_EMMC_D6                   ( G4_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_EMMC_D7                   ( G4_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_EMMC_STROBE               ( G4_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_EMMC_CLK_SET              ( G4_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_EMMC_RSTB_SET             ( G4_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_EMMC_CMD_SET              ( G4_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_EMMC_D0_SET               ( G4_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_EMMC_D1_SET               ( G4_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_EMMC_D2_SET               ( G4_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_EMMC_D3_SET               ( G4_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_EMMC_D4_SET               ( G4_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_EMMC_D5_SET               ( G4_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_EMMC_D6_SET               ( G4_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_EMMC_D7_SET               ( G4_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_EMMC_STROBE_SET           ( G4_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_EMMC_CLK_CLR              ( G4_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_EMMC_RSTB_CLR             ( G4_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_EMMC_CMD_CLR              ( G4_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_EMMC_D0_CLR               ( G4_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_EMMC_D1_CLR               ( G4_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_EMMC_D2_CLR               ( G4_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_EMMC_D3_CLR               ( G4_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_EMMC_D4_CLR               ( G4_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_EMMC_D5_CLR               ( G4_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_EMMC_D6_CLR               ( G4_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_EMMC_D7_CLR               ( G4_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_EMMC_STROBE_CLR           ( G4_PIN_REG_BASE + 0x082C )

#define REG_GROUP_PIN_EXTINT11                  ( G5_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_EXTINT7                   ( G5_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_EXTINT8                   ( G5_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_EXTINT11_SET              ( G5_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_EXTINT7_SET               ( G5_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_EXTINT8_SET               ( G5_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_EXTINT11_CLR              ( G5_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_EXTINT7_CLR               ( G5_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_EXTINT8_CLR               ( G5_PIN_REG_BASE + 0x0808 )

#define REG_GROUP_PIN_SD1_CMD                   ( G6_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_SD1_D0                    ( G6_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_SD1_D1                    ( G6_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_SD1_CLK                   ( G6_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_SD1_D2                    ( G6_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_SD1_D3                    ( G6_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SD1_CMD_SET               ( G6_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_SD1_D0_SET                ( G6_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_SD1_D1_SET                ( G6_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_SD1_CLK_SET               ( G6_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_SD1_D2_SET                ( G6_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_SD1_D3_SET                ( G6_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SD1_CMD_CLR               ( G6_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_SD1_D0_CLR                ( G6_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_SD1_D1_CLR                ( G6_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_SD1_CLK_CLR               ( G6_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_SD1_D2_CLR                ( G6_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_SD1_D3_CLR                ( G6_PIN_REG_BASE + 0x0814 )

#define REG_GROUP_PIN_KEYOUT0                   ( G7_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_KEYOUT1                   ( G7_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_KEYOUT2                   ( G7_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_KEYIN0                    ( G7_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_KEYIN1                    ( G7_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_KEYIN2                    ( G7_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SDA1                      ( G7_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_SCL1                      ( G7_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_EXTINT1                   ( G7_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_EXTINT0                   ( G7_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_EXTINT12                  ( G7_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_EXTINT15                  ( G7_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_KEYOUT0_SET               ( G7_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_KEYOUT1_SET               ( G7_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_KEYOUT2_SET               ( G7_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_KEYIN0_SET                ( G7_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_KEYIN1_SET                ( G7_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_KEYIN2_SET                ( G7_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SDA1_SET                  ( G7_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_SCL1_SET                  ( G7_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_EXTINT1_SET               ( G7_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_EXTINT0_SET               ( G7_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_EXTINT12_SET              ( G7_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_EXTINT15_SET              ( G7_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_KEYOUT0_CLR               ( G7_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_KEYOUT1_CLR               ( G7_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_KEYOUT2_CLR               ( G7_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_KEYIN0_CLR                ( G7_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_KEYIN1_CLR                ( G7_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_KEYIN2_CLR                ( G7_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_SDA1_CLR                  ( G7_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_SCL1_CLR                  ( G7_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_EXTINT1_CLR               ( G7_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_EXTINT0_CLR               ( G7_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_EXTINT12_CLR              ( G7_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_EXTINT15_CLR              ( G7_PIN_REG_BASE + 0x082C )

#define REG_GROUP_PIN_U0TXD                     ( G8_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_U0RXD                     ( G8_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_U0CTS                     ( G8_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_U0RTS                     ( G8_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_IIS0DI                    ( G8_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_IIS0DO                    ( G8_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_IIS0CLK                   ( G8_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_IIS0LRCK                  ( G8_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_CLK_AUX0                  ( G8_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_RFCTL19                   ( G8_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_RFCTL18                   ( G8_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_WIFI_COEXIST              ( G8_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_BEIDOU_COEXIST            ( G8_PIN_REG_BASE + 0x0030 )
#define REG_GROUP_PIN_MTCK_ARM                  ( G8_PIN_REG_BASE + 0x0034 )
#define REG_GROUP_PIN_MTMS_ARM                  ( G8_PIN_REG_BASE + 0x0038 )
#define REG_GROUP_PIN_MTRST_N_ARM               ( G8_PIN_REG_BASE + 0x003C )
#define REG_GROUP_PIN_MTDO_ARM                  ( G8_PIN_REG_BASE + 0x0040 )
#define REG_GROUP_PIN_MTDI_ARM                  ( G8_PIN_REG_BASE + 0x0044 )
#define REG_GROUP_PIN_U3TXD                     ( G8_PIN_REG_BASE + 0x0048 )
#define REG_GROUP_PIN_U3RXD                     ( G8_PIN_REG_BASE + 0x004C )
#define REG_GROUP_PIN_U3CTS                     ( G8_PIN_REG_BASE + 0x0050 )
#define REG_GROUP_PIN_U3RTS                     ( G8_PIN_REG_BASE + 0x0054 )
#define REG_GROUP_PIN_CLK_AUX0_SEL              ( G8_PIN_REG_BASE + 0x0058 )
#define REG_GROUP_PIN_U0TXD_SET                 ( G8_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_U0RXD_SET                 ( G8_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_U0CTS_SET                 ( G8_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_U0RTS_SET                 ( G8_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_IIS0DI_SET                ( G8_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_IIS0DO_SET                ( G8_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_IIS0CLK_SET               ( G8_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_IIS0LRCK_SET              ( G8_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_CLK_AUX0_SET              ( G8_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_RFCTL19_SET               ( G8_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_RFCTL18_SET               ( G8_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_WIFI_COEXIST_SET          ( G8_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_BEIDOU_COEXIST_SET        ( G8_PIN_REG_BASE + 0x0430 )
#define REG_GROUP_PIN_MTCK_ARM_SET              ( G8_PIN_REG_BASE + 0x0434 )
#define REG_GROUP_PIN_MTMS_ARM_SET              ( G8_PIN_REG_BASE + 0x0438 )
#define REG_GROUP_PIN_MTRST_N_ARM_SET           ( G8_PIN_REG_BASE + 0x043C )
#define REG_GROUP_PIN_MTDO_ARM_SET              ( G8_PIN_REG_BASE + 0x0440 )
#define REG_GROUP_PIN_MTDI_ARM_SET              ( G8_PIN_REG_BASE + 0x0444 )
#define REG_GROUP_PIN_U3TXD_SET                 ( G8_PIN_REG_BASE + 0x0448 )
#define REG_GROUP_PIN_U3RXD_SET                 ( G8_PIN_REG_BASE + 0x044C )
#define REG_GROUP_PIN_U3CTS_SET                 ( G8_PIN_REG_BASE + 0x0450 )
#define REG_GROUP_PIN_U3RTS_SET                 ( G8_PIN_REG_BASE + 0x0454 )
#define REG_GROUP_PIN_CLK_AUX0_SEL_SET          ( G8_PIN_REG_BASE + 0x0458 )
#define REG_GROUP_PIN_U0TXD_CLR                 ( G8_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_U0RXD_CLR                 ( G8_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_U0CTS_CLR                 ( G8_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_U0RTS_CLR                 ( G8_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_IIS0DI_CLR                ( G8_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_IIS0DO_CLR                ( G8_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_IIS0CLK_CLR               ( G8_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_IIS0LRCK_CLR              ( G8_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_CLK_AUX0_CLR              ( G8_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_RFCTL19_CLR               ( G8_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_RFCTL18_CLR               ( G8_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_WIFI_COEXIST_CLR          ( G8_PIN_REG_BASE + 0x082C )
#define REG_GROUP_PIN_BEIDOU_COEXIST_CLR        ( G8_PIN_REG_BASE + 0x0830 )
#define REG_GROUP_PIN_MTCK_ARM_CLR              ( G8_PIN_REG_BASE + 0x0834 )
#define REG_GROUP_PIN_MTMS_ARM_CLR              ( G8_PIN_REG_BASE + 0x0838 )
#define REG_GROUP_PIN_MTRST_N_ARM_CLR           ( G8_PIN_REG_BASE + 0x083C )
#define REG_GROUP_PIN_MTDO_ARM_CLR              ( G8_PIN_REG_BASE + 0x0840 )
#define REG_GROUP_PIN_MTDI_ARM_CLR              ( G8_PIN_REG_BASE + 0x0844 )
#define REG_GROUP_PIN_U3TXD_CLR                 ( G8_PIN_REG_BASE + 0x0848 )
#define REG_GROUP_PIN_U3RXD_CLR                 ( G8_PIN_REG_BASE + 0x084C )
#define REG_GROUP_PIN_U3CTS_CLR                 ( G8_PIN_REG_BASE + 0x0850 )
#define REG_GROUP_PIN_U3RTS_CLR                 ( G8_PIN_REG_BASE + 0x0854 )
#define REG_GROUP_PIN_CLK_AUX0_SEL_CLR          ( G8_PIN_REG_BASE + 0x0858 )

#define REG_GROUP_PIN_CMPD1                     ( G9_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_CMPD0                     ( G9_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_CMRST1                    ( G9_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_CMRST0                    ( G9_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_CMMCLK1                   ( G9_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_CMMCLK                    ( G9_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SDA0                      ( G9_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_SCL0                      ( G9_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_CLK_AUX2_SEL              ( G9_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_CMPD1_SET                 ( G9_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_CMPD0_SET                 ( G9_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_CMRST1_SET                ( G9_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_CMRST0_SET                ( G9_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_CMMCLK1_SET               ( G9_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_CMMCLK_SET                ( G9_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SDA0_SET                  ( G9_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_SCL0_SET                  ( G9_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_CLK_AUX2_SEL_SET          ( G9_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_CMPD1_CLR                 ( G9_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_CMPD0_CLR                 ( G9_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_CMRST1_CLR                ( G9_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_CMRST0_CLR                ( G9_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_CMMCLK1_CLR               ( G9_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_CMMCLK_CLR                ( G9_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_SDA0_CLR                  ( G9_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_SCL0_CLR                  ( G9_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_CLK_AUX2_SEL_CLR          ( G9_PIN_REG_BASE + 0x0820 )

#define REG_GROUP_PIN_RFSEN0                    ( G10_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_RFSCK0                    ( G10_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_RFSDA0                    ( G10_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_RFSEN1                    ( G10_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_RFSCK1                    ( G10_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_RFSDA1                    ( G10_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_RFFE0_SDA                 ( G10_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_RFFE0_SCK                 ( G10_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_RFFE1_SDA                 ( G10_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_RFFE1_SCK                 ( G10_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_RF_LVDS0_DAC_ON           ( G10_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_RF_LVDS0_ADC_ON           ( G10_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_RFCTL0                    ( G10_PIN_REG_BASE + 0x0030 )
#define REG_GROUP_PIN_RFCTL1                    ( G10_PIN_REG_BASE + 0x0034 )
#define REG_GROUP_PIN_RFCTL2                    ( G10_PIN_REG_BASE + 0x0038 )
#define REG_GROUP_PIN_RFCTL3                    ( G10_PIN_REG_BASE + 0x003C )
#define REG_GROUP_PIN_RFCTL4                    ( G10_PIN_REG_BASE + 0x0040 )
#define REG_GROUP_PIN_RFCTL5                    ( G10_PIN_REG_BASE + 0x0044 )
#define REG_GROUP_PIN_RFCTL6                    ( G10_PIN_REG_BASE + 0x0048 )
#define REG_GROUP_PIN_RFCTL7                    ( G10_PIN_REG_BASE + 0x004C )
#define REG_GROUP_PIN_RFCTL8                    ( G10_PIN_REG_BASE + 0x0050 )
#define REG_GROUP_PIN_RFCTL9                    ( G10_PIN_REG_BASE + 0x0054 )
#define REG_GROUP_PIN_RFCTL10                   ( G10_PIN_REG_BASE + 0x0058 )
#define REG_GROUP_PIN_RFCTL11                   ( G10_PIN_REG_BASE + 0x005C )
#define REG_GROUP_PIN_RFCTL12                   ( G10_PIN_REG_BASE + 0x0060 )
#define REG_GROUP_PIN_RFCTL13                   ( G10_PIN_REG_BASE + 0x0064 )
#define REG_GROUP_PIN_RFCTL14                   ( G10_PIN_REG_BASE + 0x0068 )
#define REG_GROUP_PIN_RFCTL15                   ( G10_PIN_REG_BASE + 0x006C )
#define REG_GROUP_PIN_RFCTL16                   ( G10_PIN_REG_BASE + 0x0070 )
#define REG_GROUP_PIN_RFCTL17                   ( G10_PIN_REG_BASE + 0x0074 )
#define REG_GROUP_PIN_RFSEN0_SET                ( G10_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_RFSCK0_SET                ( G10_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_RFSDA0_SET                ( G10_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_RFSEN1_SET                ( G10_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_RFSCK1_SET                ( G10_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_RFSDA1_SET                ( G10_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_RFFE0_SDA_SET             ( G10_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_RFFE0_SCK_SET             ( G10_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_RFFE1_SDA_SET             ( G10_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_RFFE1_SCK_SET             ( G10_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_RF_LVDS0_DAC_ON_SET       ( G10_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_RF_LVDS0_ADC_ON_SET       ( G10_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_RFCTL0_SET                ( G10_PIN_REG_BASE + 0x0430 )
#define REG_GROUP_PIN_RFCTL1_SET                ( G10_PIN_REG_BASE + 0x0434 )
#define REG_GROUP_PIN_RFCTL2_SET                ( G10_PIN_REG_BASE + 0x0438 )
#define REG_GROUP_PIN_RFCTL3_SET                ( G10_PIN_REG_BASE + 0x043C )
#define REG_GROUP_PIN_RFCTL4_SET                ( G10_PIN_REG_BASE + 0x0440 )
#define REG_GROUP_PIN_RFCTL5_SET                ( G10_PIN_REG_BASE + 0x0444 )
#define REG_GROUP_PIN_RFCTL6_SET                ( G10_PIN_REG_BASE + 0x0448 )
#define REG_GROUP_PIN_RFCTL7_SET                ( G10_PIN_REG_BASE + 0x044C )
#define REG_GROUP_PIN_RFCTL8_SET                ( G10_PIN_REG_BASE + 0x0450 )
#define REG_GROUP_PIN_RFCTL9_SET                ( G10_PIN_REG_BASE + 0x0454 )
#define REG_GROUP_PIN_RFCTL10_SET               ( G10_PIN_REG_BASE + 0x0458 )
#define REG_GROUP_PIN_RFCTL11_SET               ( G10_PIN_REG_BASE + 0x045C )
#define REG_GROUP_PIN_RFCTL12_SET               ( G10_PIN_REG_BASE + 0x0460 )
#define REG_GROUP_PIN_RFCTL13_SET               ( G10_PIN_REG_BASE + 0x0464 )
#define REG_GROUP_PIN_RFCTL14_SET               ( G10_PIN_REG_BASE + 0x0468 )
#define REG_GROUP_PIN_RFCTL15_SET               ( G10_PIN_REG_BASE + 0x046C )
#define REG_GROUP_PIN_RFCTL16_SET               ( G10_PIN_REG_BASE + 0x0470 )
#define REG_GROUP_PIN_RFCTL17_SET               ( G10_PIN_REG_BASE + 0x0474 )
#define REG_GROUP_PIN_RFSEN0_CLR                ( G10_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_RFSCK0_CLR                ( G10_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_RFSDA0_CLR                ( G10_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_RFSEN1_CLR                ( G10_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_RFSCK1_CLR                ( G10_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_RFSDA1_CLR                ( G10_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_RFFE0_SDA_CLR             ( G10_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_RFFE0_SCK_CLR             ( G10_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_RFFE1_SDA_CLR             ( G10_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_RFFE1_SCK_CLR             ( G10_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_RF_LVDS0_DAC_ON_CLR       ( G10_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_RF_LVDS0_ADC_ON_CLR       ( G10_PIN_REG_BASE + 0x082C )
#define REG_GROUP_PIN_RFCTL0_CLR                ( G10_PIN_REG_BASE + 0x0830 )
#define REG_GROUP_PIN_RFCTL1_CLR                ( G10_PIN_REG_BASE + 0x0834 )
#define REG_GROUP_PIN_RFCTL2_CLR                ( G10_PIN_REG_BASE + 0x0838 )
#define REG_GROUP_PIN_RFCTL3_CLR                ( G10_PIN_REG_BASE + 0x083C )
#define REG_GROUP_PIN_RFCTL4_CLR                ( G10_PIN_REG_BASE + 0x0840 )
#define REG_GROUP_PIN_RFCTL5_CLR                ( G10_PIN_REG_BASE + 0x0844 )
#define REG_GROUP_PIN_RFCTL6_CLR                ( G10_PIN_REG_BASE + 0x0848 )
#define REG_GROUP_PIN_RFCTL7_CLR                ( G10_PIN_REG_BASE + 0x084C )
#define REG_GROUP_PIN_RFCTL8_CLR                ( G10_PIN_REG_BASE + 0x0850 )
#define REG_GROUP_PIN_RFCTL9_CLR                ( G10_PIN_REG_BASE + 0x0854 )
#define REG_GROUP_PIN_RFCTL10_CLR               ( G10_PIN_REG_BASE + 0x0858 )
#define REG_GROUP_PIN_RFCTL11_CLR               ( G10_PIN_REG_BASE + 0x085C )
#define REG_GROUP_PIN_RFCTL12_CLR               ( G10_PIN_REG_BASE + 0x0860 )
#define REG_GROUP_PIN_RFCTL13_CLR               ( G10_PIN_REG_BASE + 0x0864 )
#define REG_GROUP_PIN_RFCTL14_CLR               ( G10_PIN_REG_BASE + 0x0868 )
#define REG_GROUP_PIN_RFCTL15_CLR               ( G10_PIN_REG_BASE + 0x086C )
#define REG_GROUP_PIN_RFCTL16_CLR               ( G10_PIN_REG_BASE + 0x0870 )
#define REG_GROUP_PIN_RFCTL17_CLR               ( G10_PIN_REG_BASE + 0x0874 )

#define REG_GROUP_PIN_SD2_CMD                   ( G11_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_SD2_D0                    ( G11_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_SD2_D1                    ( G11_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_SD2_CLK                   ( G11_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_SD2_D2                    ( G11_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_SD2_D3                    ( G11_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SD2_CMD_SET               ( G11_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_SD2_D0_SET                ( G11_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_SD2_D1_SET                ( G11_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_SD2_CLK_SET               ( G11_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_SD2_D2_SET                ( G11_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_SD2_D3_SET                ( G11_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SD2_CMD_CLR               ( G11_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_SD2_D0_CLR                ( G11_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_SD2_D1_CLR                ( G11_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_SD2_CLK_CLR               ( G11_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_SD2_D2_CLR                ( G11_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_SD2_D3_CLR                ( G11_PIN_REG_BASE + 0x0814 )

#define REG_GROUP_PIN_U4TXD                     ( G12_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_U4RXD                     ( G12_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_U2TXD                     ( G12_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_U2RXD                     ( G12_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_U1TXD                     ( G12_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_U1RXD                     ( G12_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SDA4                      ( G12_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_SCL4                      ( G12_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_SCL2                      ( G12_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_SDA2                      ( G12_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_IIS3DI                    ( G12_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_IIS3DO                    ( G12_PIN_REG_BASE + 0x002C )
#define REG_GROUP_PIN_IIS3CLK                   ( G12_PIN_REG_BASE + 0x0030 )
#define REG_GROUP_PIN_IIS3LRCK                  ( G12_PIN_REG_BASE + 0x0034 )
#define REG_GROUP_PIN_IIS1DI                    ( G12_PIN_REG_BASE + 0x0038 )
#define REG_GROUP_PIN_IIS1DO                    ( G12_PIN_REG_BASE + 0x003C )
#define REG_GROUP_PIN_IIS1CLK                   ( G12_PIN_REG_BASE + 0x0040 )
#define REG_GROUP_PIN_IIS1LRCK                  ( G12_PIN_REG_BASE + 0x0044 )
#define REG_GROUP_PIN_SPI0_CSN                  ( G12_PIN_REG_BASE + 0x0048 )
#define REG_GROUP_PIN_SPI0_DO                   ( G12_PIN_REG_BASE + 0x004C )
#define REG_GROUP_PIN_SPI0_DI                   ( G12_PIN_REG_BASE + 0x0050 )
#define REG_GROUP_PIN_SPI0_CLK                  ( G12_PIN_REG_BASE + 0x0054 )
#define REG_GROUP_PIN_U4TXD_SET                 ( G12_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_U4RXD_SET                 ( G12_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_U2TXD_SET                 ( G12_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_U2RXD_SET                 ( G12_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_U1TXD_SET                 ( G12_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_U1RXD_SET                 ( G12_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SDA4_SET                  ( G12_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_SCL4_SET                  ( G12_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_SCL2_SET                  ( G12_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_SDA2_SET                  ( G12_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_IIS3DI_SET                ( G12_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_IIS3DO_SET                ( G12_PIN_REG_BASE + 0x042C )
#define REG_GROUP_PIN_IIS3CLK_SET               ( G12_PIN_REG_BASE + 0x0430 )
#define REG_GROUP_PIN_IIS3LRCK_SET              ( G12_PIN_REG_BASE + 0x0434 )
#define REG_GROUP_PIN_IIS1DI_SET                ( G12_PIN_REG_BASE + 0x0438 )
#define REG_GROUP_PIN_IIS1DO_SET                ( G12_PIN_REG_BASE + 0x043C )
#define REG_GROUP_PIN_IIS1CLK_SET               ( G12_PIN_REG_BASE + 0x0440 )
#define REG_GROUP_PIN_IIS1LRCK_SET              ( G12_PIN_REG_BASE + 0x0444 )
#define REG_GROUP_PIN_SPI0_CSN_SET              ( G12_PIN_REG_BASE + 0x0448 )
#define REG_GROUP_PIN_SPI0_DO_SET               ( G12_PIN_REG_BASE + 0x044C )
#define REG_GROUP_PIN_SPI0_DI_SET               ( G12_PIN_REG_BASE + 0x0450 )
#define REG_GROUP_PIN_SPI0_CLK_SET              ( G12_PIN_REG_BASE + 0x0454 )
#define REG_GROUP_PIN_U4TXD_CLR                 ( G12_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_U4RXD_CLR                 ( G12_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_U2TXD_CLR                 ( G12_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_U2RXD_CLR                 ( G12_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_U1TXD_CLR                 ( G12_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_U1RXD_CLR                 ( G12_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_SDA4_CLR                  ( G12_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_SCL4_CLR                  ( G12_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_SCL2_CLR                  ( G12_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_SDA2_CLR                  ( G12_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_IIS3DI_CLR                ( G12_PIN_REG_BASE + 0x0828 )
#define REG_GROUP_PIN_IIS3DO_CLR                ( G12_PIN_REG_BASE + 0x082C )
#define REG_GROUP_PIN_IIS3CLK_CLR               ( G12_PIN_REG_BASE + 0x0830 )
#define REG_GROUP_PIN_IIS3LRCK_CLR              ( G12_PIN_REG_BASE + 0x0834 )
#define REG_GROUP_PIN_IIS1DI_CLR                ( G12_PIN_REG_BASE + 0x0838 )
#define REG_GROUP_PIN_IIS1DO_CLR                ( G12_PIN_REG_BASE + 0x083C )
#define REG_GROUP_PIN_IIS1CLK_CLR               ( G12_PIN_REG_BASE + 0x0840 )
#define REG_GROUP_PIN_IIS1LRCK_CLR              ( G12_PIN_REG_BASE + 0x0844 )
#define REG_GROUP_PIN_SPI0_CSN_CLR              ( G12_PIN_REG_BASE + 0x0848 )
#define REG_GROUP_PIN_SPI0_DO_CLR               ( G12_PIN_REG_BASE + 0x084C )
#define REG_GROUP_PIN_SPI0_DI_CLR               ( G12_PIN_REG_BASE + 0x0850 )
#define REG_GROUP_PIN_SPI0_CLK_CLR              ( G12_PIN_REG_BASE + 0x0854 )

#define REG_GROUP_PIN_SIMCLK2                   ( G13_PIN_REG_BASE + 0x0000 )
#define REG_GROUP_PIN_SIMDA2                    ( G13_PIN_REG_BASE + 0x0004 )
#define REG_GROUP_PIN_SIMRST2                   ( G13_PIN_REG_BASE + 0x0008 )
#define REG_GROUP_PIN_SIMCLK1                   ( G13_PIN_REG_BASE + 0x000C )
#define REG_GROUP_PIN_SIMDA1                    ( G13_PIN_REG_BASE + 0x0010 )
#define REG_GROUP_PIN_SIMRST1                   ( G13_PIN_REG_BASE + 0x0014 )
#define REG_GROUP_PIN_SIMCLK0                   ( G13_PIN_REG_BASE + 0x0018 )
#define REG_GROUP_PIN_SIMDA0                    ( G13_PIN_REG_BASE + 0x001C )
#define REG_GROUP_PIN_SIMRST0                   ( G13_PIN_REG_BASE + 0x0020 )
#define REG_GROUP_PIN_SIM_MS                    ( G13_PIN_REG_BASE + 0x0024 )
#define REG_GROUP_PIN_CLK_AUX1_SEL              ( G13_PIN_REG_BASE + 0x0028 )
#define REG_GROUP_PIN_SIMCLK2_SET               ( G13_PIN_REG_BASE + 0x0400 )
#define REG_GROUP_PIN_SIMDA2_SET                ( G13_PIN_REG_BASE + 0x0404 )
#define REG_GROUP_PIN_SIMRST2_SET               ( G13_PIN_REG_BASE + 0x0408 )
#define REG_GROUP_PIN_SIMCLK1_SET               ( G13_PIN_REG_BASE + 0x040C )
#define REG_GROUP_PIN_SIMDA1_SET                ( G13_PIN_REG_BASE + 0x0410 )
#define REG_GROUP_PIN_SIMRST1_SET               ( G13_PIN_REG_BASE + 0x0414 )
#define REG_GROUP_PIN_SIMCLK0_SET               ( G13_PIN_REG_BASE + 0x0418 )
#define REG_GROUP_PIN_SIMDA0_SET                ( G13_PIN_REG_BASE + 0x041C )
#define REG_GROUP_PIN_SIMRST0_SET               ( G13_PIN_REG_BASE + 0x0420 )
#define REG_GROUP_PIN_SIM_MS_SET                ( G13_PIN_REG_BASE + 0x0424 )
#define REG_GROUP_PIN_CLK_AUX1_SEL_SET          ( G13_PIN_REG_BASE + 0x0428 )
#define REG_GROUP_PIN_SIMCLK2_CLR               ( G13_PIN_REG_BASE + 0x0800 )
#define REG_GROUP_PIN_SIMDA2_CLR                ( G13_PIN_REG_BASE + 0x0804 )
#define REG_GROUP_PIN_SIMRST2_CLR               ( G13_PIN_REG_BASE + 0x0808 )
#define REG_GROUP_PIN_SIMCLK1_CLR               ( G13_PIN_REG_BASE + 0x080C )
#define REG_GROUP_PIN_SIMDA1_CLR                ( G13_PIN_REG_BASE + 0x0810 )
#define REG_GROUP_PIN_SIMRST1_CLR               ( G13_PIN_REG_BASE + 0x0814 )
#define REG_GROUP_PIN_SIMCLK0_CLR               ( G13_PIN_REG_BASE + 0x0818 )
#define REG_GROUP_PIN_SIMDA0_CLR                ( G13_PIN_REG_BASE + 0x081C )
#define REG_GROUP_PIN_SIMRST0_CLR               ( G13_PIN_REG_BASE + 0x0820 )
#define REG_GROUP_PIN_SIM_MS_CLR                ( G13_PIN_REG_BASE + 0x0824 )
#define REG_GROUP_PIN_CLK_AUX1_SEL_CLR          ( G13_PIN_REG_BASE + 0x0828 )

/* bits definitions for register REG_PIN_XXX */
#define BITS_PIN_DS(_x_)                ( ((_x_) << 19) & (BIT_19|BIT_20|BIT_21) )
#define BIT_PIN_SLP_AONSYS              ( BIT_16 )
#define BIT_PIN_SLP_WTLCP               ( BIT_15 )
#define BIT_PIN_SLP_PUBCP               ( BIT_14 )
#define BIT_PIN_SLP_AP                  ( BIT_13 )
#define BIT_PIN_SLP_NONE		( (~(0xf << 13)) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_ISO_VALUE		( BIT_8 )
#define BIT_PIN_WPU                     ( BIT_7 )
#define BIT_PIN_WPD                     ( BIT_6 )
#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_PIN_SLP_WPU                 ( BIT_3 )
#define BIT_PIN_SLP_WPD                 ( BIT_2 )
#define BIT_PIN_SLP_IE                  ( BIT_1 )
#define BIT_PIN_SLP_OE                  ( BIT_0 )

/* vars definitions for controller CTL_PIN */
#define BIT_PIN_NUL                     ( 0 )
#define BIT_PIN_SLP_NUL                 ( 0 )
#define BIT_PIN_SLP_Z                   ( 0 )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPUS                    ( BIT_12 )
#define BIT_PIN_NULL                    ( 0 )


// CFIO --------
#define BITS_DEF(_x_)		    ( ((_x_) << 22) & (BIT_22|BIT_23|BIT_24|BIT_25|BIT_26|BIT_27|BIT_28|BIT_29) )//BIT22~BIT29 keep default value
//#define BITS_HYSCTL(_x_)		( ((_x_) << 28) & (BIT_28|BIT_29) )//CFIO
//#define BIT_NSTATICEN		    ( BIT_27 )//CFIO
//#define BIT_PSTATICEN		    ( BIT_26 )//CFIO
//#define BITS_NSLEW(_x_)		    ( ((_x_) << 24) & (BIT_24|BIT_25) )//CFIO
//#define BITS_PSLEW(_x_)		    ( ((_x_) << 22) & (BIT_22|BIT_23) )//CFIO
//#define BITS_NSTR(_x_)		( ((_x_) << 20) & (BIT_20|BIT_21) )
//#define BITS_PSTR(_x_)		( ((_x_) << 18) & (BIT_18|BIT_19) )
#define BITS_STR(_x_)				((((_x_) << 18) & (BIT_18|BIT_19))|(((_x_) << 20) & (BIT_20|BIT_21)))//CFIO
#define BIT_SLP_AONSYS              ( BIT_16 )
#define BIT_SLP_WTLCP               ( BIT_15 )
#define BIT_SLP_PUBCP               ( BIT_14 )
#define BIT_SLP_AP                  ( BIT_13 )
#define BIT_SLP_NONE		( (~(0xf << 13)) & (BIT_13|BIT_14|BIT_15|BIT_16) )
#define BIT_WPUS		        ( BIT_12 )
#define BIT_WPD2                ( BIT_11 )
#define BIT_WPUS2               ( BIT_10 )
#define BIT_POC				    ( BIT_9 )
#define BIT_ISO_VALUE		    ( BIT_8 )
#define BIT_WPU			( BIT_7 )
#define BIT_WPD 		( BIT_6 )
#define BITS_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_SLP_WPU                 ( BIT_3 )
#define BIT_SLP_WPD                 ( BIT_2 )
#define BIT_SLP_IE                  ( BIT_1 )
#define BIT_SLP_OE                  ( BIT_0 )
#define BIT_SLP_NUL                   ( 0 )
#define BIT_NUL                     ( 0 )
#define BIT_SLP_Z                   ( 0 )
#endif
#endif //_PINMAP_H_

